ROFL RLY .-.
>_>
<_<
engineer: alrighty then
and don't bother looking in the dolphin src...
(unless maybe it's just that mine's outdated)
but the IREF structure doesn't have anything defined...
it's just:
case BPMEM_IREF:
/*commenting
commenting
and more commenting*/
that's it 
@Dolphin Team: I want a refund NOW!
(lol... I Turtle'd the SVN)
Found it:
/*---------------------------------------------------------------------------*/
//
// Name: GDSetIndTexOrder
//
// Desc: Associates direct texture maps and coordinate names
// with indirect texture maps.
//
// Arguments: texCoord0: Associated texcoord for indirect texture 0.
// texMap0: Associated texture map for indirect texture 0.
// texCoord1: Associated texcoord for indirect texture 1.
// texMap1: Associated texture map for indirect texture 1.
// texCoord2: Associated texcoord for indirect texture 2.
// texMap2: Associated texture map for indirect texture 2.
// texCoord3: Associated texcoord for indirect texture 3.
// texMap3: Associated texture map for indirect texture 3.
//
/*---------------------------------------------------------------------------*/
void GDSetIndTexOrder (
GXTexCoordID texCoord0,
GXTexMapID texMap0,
GXTexCoordID texCoord1,
GXTexMapID texMap1,
GXTexCoordID texCoord2,
GXTexMapID texMap2,
GXTexCoordID texCoord3,
GXTexMapID texMap3 )
{
GDWriteBPCmd( RAS1_IREF(
(texMap0 & 7),
(texCoord0 & 7),
(texMap1 & 7),
(texCoord1 & 7),
(texMap2 & 7),
(texCoord2 & 7),
(texMap3 & 7),
(texCoord3 & 7),
RAS1_IREF_ID) );
}
/*
* ras1_iref struct
*/
#define RAS1_IREF_BI0_SHIFT 0
#define RAS1_IREF_BC0_SHIFT 3
#define RAS1_IREF_BI1_SHIFT 6
#define RAS1_IREF_BC1_SHIFT 9
#define RAS1_IREF_BI2_SHIFT 12
#define RAS1_IREF_BC2_SHIFT 15
#define RAS1_IREF_BI3_SHIFT 18
#define RAS1_IREF_BC3_SHIFT 21
#define RAS1_IREF_RID_SHIFT 24
#define RAS1_IREF(bi0, bc0, bi1, bc1, bi2, bc2, bi3, bc3, rid) \
((((unsigned long)(bi0)) << RAS1_IREF_BI0_SHIFT) | \
(((unsigned long)(bc0)) << RAS1_IREF_BC0_SHIFT) | \
(((unsigned long)(bi1)) << RAS1_IREF_BI1_SHIFT) | \
(((unsigned long)(bc1)) << RAS1_IREF_BC1_SHIFT) | \
(((unsigned long)(bi2)) << RAS1_IREF_BI2_SHIFT) | \
(((unsigned long)(bc2)) << RAS1_IREF_BC2_SHIFT) | \
(((unsigned long)(bi3)) << RAS1_IREF_BI3_SHIFT) | \
(((unsigned long)(bc3)) << RAS1_IREF_BC3_SHIFT) | \
(((unsigned long)(rid)) << RAS1_IREF_RID_SHIFT))
It apparently has to do with indirect textures.
Edit: Already done coding bit shifts!
[StructLayout(LayoutKind.Sequential, Pack = 1)]
public struct RAS1_IRef //For indirect textures
{
//0000 0000 0000 0000 0000 0111 BI0
//0000 0000 0000 0000 0011 1000 BC0
//0000 0000 0000 0001 1100 0000 BI1
//0000 0000 0000 1110 0000 0000 BC1
//0000 0000 0111 0000 0000 0000 BI2
//0000 0011 1000 0000 0000 0000 BC2
//0001 1100 0000 0000 0000 0000 BI3
//1110 0000 0000 0000 0000 0000 BC3
public Int24 data;
public int TexMap0 { get { return (int)data & 7; } }
public int TexCoord0 { get { return ((int)data >> 3) & 7; } }
public int TexMap1 { get { return ((int)data >> 6) & 7; } }
public int TexCoord1 { get { return ((int)data >> 9) & 7; } }
public int TexMap2 { get { return ((int)data >> 12) & 7; } }
public int TexCoord2 { get { return ((int)data >> 15) & 7; } }
public int TexMap3 { get { return ((int)data >> 18) & 7; } }
public int TexCoord3 { get { return ((int)data >> 21) & 7; } }
public RAS1_IRef(byte dat0, byte dat1, byte dat2) { data._dat0 = dat0; data._dat1 = dat1; data._dat2 = dat2; }
public RAS1_IRef(int value) { data = (Int24)value; }
public RAS1_IRef(Int24 value) { data = value; }
public static int Shift(int bi0, int bc0, int bi1, int bc1, int bi2, int bc2, int bi3, int bc3)
{
return (bi0) |
((bc0) << 3) |
((bi1) << 6) |
((bc1) << 9) |
((bi2) << 12) |
((bc2) << 15) |
((bi3) << 18) |
((bc3) << 21);
}
}
